1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a transflective liquid crystal display (LCD) device implementing selectable reflective and transmissive modes.
2. Discussion of the Related Art
Generally, a transflective LCD device has advantages of both a transmissive LCD device and a reflective LCD device. Because the transflective LCD device uses a back light as well as an ambient light source, it is not dependent upon exterior light source conditions, and consumes relatively low power.
FIG. 1 is an exploded perspective view illustrating a typical transflective LCD device. The transflective LCD device 11 includes an upper substrate 15 and a lower substrate 21 that are opposed to each other, and a liquid crystal layer 23 interposed therebetween. The upper substrate 15 and the lower substrate 21 are called a color filter substrate and an array substrate, respectively. On the upper substrate 15, a black matrix 16 and a color filter layer 17 including a plurality of red (R), green (G), and blue (B) color filters are formed. The black matrix 16 surrounds each color filter such that an array matrix feature is formed. Further on the upper substrate 15, a common electrode 13 is formed to cover the color filter layer 17 and the black matrix 16.
On the lower substrate 21 opposing the upper substrate 15, thin film transistors (TFTs) “T”, as switching elements, are formed in shape of an array matrix corresponding to the color filter layer 17. In addition, a plurality of crossing gate and data lines 25 and 27 are positioned such that each TFT “T” is located near each crossing portion of the gate and data lines 25 and 27. The crossing gate and data lines define a pixel region “P”. On the pixel region “P”, a pixel electrode 19 is formed. The pixel electrode 19 includes a transmissive portion “A” and a reflective portion “C”.
FIG. 2 is a schematic cross-sectional view illustrating operation modes of the typical transflective LCD device 11. As shown, the transflective LCD device 11 includes the upper substrate 15 having the common electrode 13, the lower substrate 21 having the pixel electrode 19, the liquid crystal layer 23 interposed therebetween, and a back light 41 disposed below the lower substrate 21. The pixel electrode 19 includes a reflective electrode 19b having a through-hole “A” and a transparent electrode 19a positioned below the reflective electrode 19b. The transparent electrode 19a is separated from the reflective electrode 19b by a passivation layer 20 interposed therebetween.
For a reflective mode, the transflective LCD device 11 uses a first ray “B” of ambient light, which may radiate from an exterior natural light source or from an exterior artificial light source. The first ray “B” passes through the upper substrate 15 and is reflected by the reflective electrode 19b back through the liquid crystal layer 23, which is aligned by the application of an electric field between the reflective electrode 19b and the common electrode 13. Accordingly, the aligned liquid crystal layer 23 controls the first ray “B” so as to display an image.
For a transmissive mode, the transflective LCD device 11 uses a second ray “F” of light, which radiates from the back light 41. The second ray “F” sequentially passes through the transparent electrode 19a, the through-hole “A” of reflective electrodes 19b and the liquid crystal layer 23 which is aligned by the application of an electric field between the transparent electrode 19a and the common electrode 13. Accordingly, the aligned liquid crystal layer 23 controls the second ray “F” so as to display an image.
FIG. 3 is an expanded plan view illustrating a portion of an array substrate for a conventional transflective LCD device. As shown in FIG. 3, gate lines 25 are arranged in a transverse direction, and data lines 27 are arranged perpendicular to the gate lines 25. Both the gate lines 25 and the data lines 27 are formed upon an array substrate 21 (in FIG. 1), and a pair of gate lines 25 and data lines 27 define a pixel region “P”. Each of thin film transistors (TFTs) “T” is arranged at a position where both the gate line 25 and the data line 27 cross one another. A pixel electrode 19 comprising both a transparent electrode 19a and a reflective electrode 19b is disposed on the pixel region “P” defined by the gate line 25 and data line 27.
Each TFT “T” includes a gate electrode 32 to which a scanning signal is applied, a source electrode 33 to which a video signal is applied, and a drain electrode 35 which inputs the video signal to the pixel electrode 19. Further, each TFT “T” includes an active layer 34 between the source electrode 33 and the drain electrode 35. A portion of the gate line 25 defines a storage capacitor “S” with a portion of the pixel electrode 19. Furthermore, gate pads 29 and data pads 31 are respectively disposed at end portions of gate lines 25 and data lines 27. The gate pads 29 and the data pads 31 are to be electrically connected with a drive IC (not shown).
Still referring to FIG. 3, the pixel electrode 19 is a transflective electrode having both the transparent electrode 19a and the reflective electrode 19b. Specifically, the transparent electrode 19a is first formed on the pixel region “P”, and is electrically connected with the drain electrode 35. Then, the reflective electrode 19b is formed over the transparent electrode 19a, and is also electrically connected with the drain electrode 35 via the transparent electrode 19a. Thus, the reflective electrode 19b has a through hole “A” corresponding to a transmissive portion of the LCD device 11 such that rays of back light 41 (in FIG. 2) can pass through the through hole “A” for function in the transmissive mode. Portion “C” of the reflective electrode 19b serves as a reflective portion of the LCD device 11 such that rays of the ambient light are thereby reflected.
In the above-mentioned structure, however, two patterning processes are respectively required when forming the transparent electrode 19a and the reflective electrode 19b. At this time of patterning, the transparent electrode 19a and the reflective electrode 19b are corroded by an etching solution due to Galvanic corrosion. Accordingly, to solve this problem, an insulator (e.g., the passivation layer 20 of FIG. 2) is interposed between the transparent electrode 19a and the reflective electrode 19b. 
With reference to FIGS. 4A to 4D, 5A to 5D and 6A to 6D, a fabrication process for the conventional array substrate is explained. FIGS. 4A to 4D are sequential cross-sectional views taken along line IV—IV of FIG. 3, FIGS. 5A to 5D are sequential cross-sectional views taken along line V—V of FIG. 3, and FIGS. 6A to 6D are sequential cross-sectional views taken along line VI—VI of FIG. 3.
At first, as shown in FIGS. 4A, 5A and 6A, a first metal is deposited and patterned upon a transparent substrate 21 such that a gate pad 29, a gate line 25, and a gate electrode 32 are formed. For the first metal, aluminum (Al) or aluminum neodymium (AlNd) is conventionally employed. The gate line 25 extends from and is connected with the gate pad 29, and the gate electrode 32 protrudes from the gate line 25 (in FIG. 3). Thereafter, a gate-insulting layer 43 is formed on the transparent substrate 21 to cover the metal layer previously formed. The gate-insulating layer 43 may be an inorganic substance, such as silicon nitride (SiNx) or silicon oxide (SiO2). Subsequently, amorphous silicon (a-Si) and impurity-doped amorphous silicon (n+/p+a-Si) are formed in series on the gate-insulating layer 43. The amorphous silicon and impurity-doped amorphous silicon are simultaneously patterned to form an active layer 34 and an ohmic contact layer 47, respectively. The active layer 34 is formed on the gate-insulating layer 43, particularly over the gate electrode 32 and the ohmic contact layer 47 is formed on the active layer 34. Also, a source electrode 33 and a drain electrode 35 are formed of a second metal on the ohmic contact layer 47. By depositing and patterning this second metal, not only are the source electrode 33 and the drain electrode 35 formed, but the data line 27, a capacitor electrode 49 and a data pad 31 are also formed on the gate-insulating layer 43 such that the source electrode 33 extends from the data line 27. The source electrode 33 and the drain electrode 35 are spaced apart from each other and respectively overlap opposite ends of the gate electrode 32. The capacitor electrode 49 overlaps a portion of the gate line 25 to define the storage capacitor “S” of FIG. 3. Moreover, a portion of the ohmic contact layer 47 between the source electrode 33 and drain electrode 35 is eliminated to form a channel region “CH.”
Now referring to FIGS. 4B, 5B and 6B, a first passivation layer 51 is formed on and over the above-mentioned intermediates by depositing an organic substance such as BCB (benzocyclobutene) or an acryl-based resin. By patterning the first passivation layer 51, a first drain contact hole 53 that exposes a portion of the drain electrode 35 is formed. At this time, a first capacitor contact hole 57 and a first data pad contact hole 61 are also formed by patterning the first passivation layer 51. Furthermore, by patterning both the first passivation layer 51 and the gate-insulating layer 43, an etching hole 55 corresponding to the through-hole “A” and a first gate pad contact hole 59 are formed. The first capacitor contact hole 57 exposes a portion of the capacitor electrode 49, the first gate pad contact hole 59 exposes a portion of the gate pad 29, and the first data pad contact hole 61 exposes a portion of the data pad 31. Thereafter, a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited upon the first passivation layer 51 having the holes and subsequently patterned to form a transparent electrode 19a, a gate pad terminal 65 and a data pad terminal 67. The transparent electrode 19a electrically contacts the drain electrode 35 through the first drain contact hole 53, and the gate pad terminal 65 electrically contacts the gate pad 29 through the first gate pad contact hole 59. Additionally, the data pad terminal 67 electrically contacts the data pad 31 through the first data pad contact hole 61. At this point, the transparent electrode 19a preferably overlaps portions of the gate line 25 and contacts the capacitor electrode 49, and thus the transparent electrode 19a and the capacitor electrode 49 acts as one capacitor electrode in the storage capacitor “S”. Further, a portion of the gate line 25 acts as the other capacitor electrode in the storage capacitor “S”.
Next, as shown in FIGS. 4C, 5C and 6C, an insulating material such as silicon oxide, for example, is deposited upon the transparent electrode 19a and subsequently patterned to form a second passivation layer 69. The second passivation layer 69 comprises a second drain contact hole 53a positioned over the drain electrode 35 and a second capacitor contact hole 57a over the capacitor electrode 49. Thereafter, a third metal is deposited upon the second passivation layer 69 and subsequently patterned to form a reflective electrode 19b having a through-hole “A”. The third metal is preferably aluminum (Al) or aluminum alloy (e.g., aluminum neodymium (AlNd)) which have low resistance and high reflectance properties. The reflective electrode 19b electrically contacts the transparent electrode 19a via the second drain contact hole 53a and second capacitor contact hole 57a such that the reflective electrode 19b and the drain electrode 65 are electrically interconnected. Namely, a first portion of the reflective electrode 19b is electrically connected with the drain electrode 35 through the second drain contact hole 53a, and a second portion of the reflective electrode 19b is electrically connected with the capacitor electrode 49 through the second capacitor contact hole 57a. 
Next, referring to FIGS. 4D, 5D and 6D, exposed portions of the second passivation layer 69 are patterned to form a second gate pad contact hole 59a over the gate pad 29 and a second data pad contact hole 61a over the data pad 31. Therefore, the conventional array substrate for the LCD device is complete.
In the above-mentioned structure, the reason for forming the etching hole 55 corresponding the through-hole “A” is to get the uniform color purity of the light in both the transmissive mode and reflective mode. Namely, by matching the light-passing distances between the transmissive mode and reflective mode, the uniform color purity is achieved regardless of whether the ambient light is reflected in the reflective portion “C” or the artificial light passes through the transmissive portion “A” (i.e., through-hole).
Further, since the second passivation layer 69 is disposed between the transparent electrode 19a and the reflective electrode 19b, the electrode corrosion caused by the etching solution (that etches the reflective electrode 19b) is prevented. Namely, Galvanic corrosion caused by the etching solution between the transparent electrode 19a and the reflective electrode 19b does not occur due to the fact that the second passivation layer 69 prevents the corrosion of the transparent electrode 19a. Now the mechanism wherein the corrosion is prevented will be described below.
As well known, the equilibrium potential (oxidation potential) of the anode reaction of aluminum (Al) is lower than the equilibrium potential (reduction potential) of the cathode reaction of the transparent electrode, e.g., ITO or IZO. As a result, when Al and ITO/IZO are brought into contact with each other and immersed in the etching solution for the reflective electrode, the Al and the ITO/IZO exchange electrons therebetween while Galvanic corrosion proceeds in the interfaces between the Al, the etching solution and the ITO.
However, when forming the passivation layer 69 between the transparent electrode 19a and the reflective electrode 19b, although Galvanic corrosion is prevented, additional processes, such as mask processes and patterning processes, are required. Namely, the second passivation layer 69, as shown in FIG. 4D, is patterned to open the gate pad terminal 65 and the data pad terminal 67.
Furthermore, if the gate-insulating layer 43 and the first passivation layer 51 are not formed properly, these insulator (the gate-insulating layer 43 and the first passivation layer 51) have defects such as cracks and pin-holes therein. Thus, when etching the transparent conductive material (ITO or IZO) to form the transparent electrode 19a, the corrosion of the transparent material occurs due to the etching solution for the transparent conductive material. Namely, it is supposed that the transparent conductive material and the etching solution make contacts with the aluminum (patterned first metal) through pin-holes or the like formed in the gate-insulating layer and the first passivation layer.
Accordingly, as mentioned before, the conventional array substrate needs additional fabricating processes and consumes more time and costs, and the gate line reacts with the transparent conductive material when defects are formed in the insulators, thereby decreasing the manufacturing yield of the LCD device.